Embodiments exemplarily described herein relate to a semiconductor device, and more particularly, to a semiconductor device including active fins and a method of manufacturing the same.
In recent years, the downscaling of semiconductor devices has rapidly progressed. Also, since the semiconductor devices require not only high operating speeds but also accurate operations, research has been variously conducted into optimizing structures of transistors included in the semiconductor devices. In particular, multi-gate transistors have been proposed as a scaling technique for increasing the density of integrated circuit (IC) devices. In the multi-gate transistor, an active fin is formed on a substrate, and a gate is formed on the active fin. Since the multi-gate transistor uses a three-dimensional (3D) channel, it is easy to scale the multi-gate transistor. Also, even if a gate length is not increased, current controllability may be improved. Furthermore, a short channel effect (SCE), which may affect an electric potential of a channel region due to a drain voltage, may be effectively inhibited.